Occlusion Culling and Hardware Accelerated Volume Rendering

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dc.contributor.advisor Strasser, Wolfgang de_DE
dc.contributor.author Meissner, Michael de_DE
dc.date.accessioned 2001-09-18 de_DE
dc.date.accessioned 2014-03-18T10:09:09Z
dc.date.available 2001-09-18 de_DE
dc.date.available 2014-03-18T10:09:09Z
dc.date.issued 2000 de_DE
dc.identifier.other 09502168X de_DE
dc.identifier.uri http://nbn-resolving.de/urn:nbn:de:bsz:21-opus-2926 de_DE
dc.identifier.uri http://hdl.handle.net/10900/48189
dc.description.abstract Within this dissertation, a set of algorithmic optimizations are developed, enabling significant performance improvements due to a much better utilization of the available bandwidth. Additionally, new architectural concepts circumventing the bottle-necks of currently available general purpose graphics hardware are presented. In the field of polygon rendering, a unique mechanism for hardware supported occlusion queries to cull geometry prior to geometry transformation --- saving bandwidth on the front bus --- is presented. As an orthogonal addition to this, a novel visibility driven rasterization scheme is presented, saving processing cycles within the pipeline by culling occluded geometry prior to rasterization. Thus, more objects can be rendered or more cycles can be spent on multi-pass rendering of the potentially visible objects. With respect to volume rendering, this dissertation contributes the first side by side comparison of different volume rendering algorithms identifying each algorithm's strengths and weaknesses. Furthermore, new techniques for using polygon graphics hardware and multi-pass rendering are presented, enabling the combination of shading and classification of volume data. Additionally, minor modifications to the data path are proposed such that multi-pass rendering can be avoided, thus increasing the overall achievable frame-rate. Furthermore, we demonstrate how to efficiently use general purpose hardware (a single-chip SIMD architecture) for volume rendering, providing much more flexibility than dedicated polygon graphics hardware. As a summary of the above described work, a novel low-cost special purpose hardware architecture that achieves superior image quality while providing an incomparable degree of flexibility is presented. de_DE
dc.description.abstract Within this dissertation, a set of algorithmic optimizations are developed, enabling significant performance improvements due to a much better utilization of the available bandwidth. Additionally, new architectural concepts circumventing the bottle-necks of currently available general purpose graphics hardware are presented. In the field of polygon rendering, a unique mechanism for hardware supported occlusion queries to cull geometry prior to geometry transformation --- saving bandwidth on the front bus --- is presented. As an orthogonal addition to this, a novel visibility driven rasterization scheme is presented, saving processing cycles within the pipeline by culling occluded geometry prior to rasterization. Thus, more objects can be rendered or more cycles can be spent on multi-pass rendering of the potentially visible objects. With respect to volume rendering, this dissertation contributes the first side by side comparison of different volume rendering algorithms identifying each algorithm's strengths and weaknesses. Furthermore, new techniques for using polygon graphics hardware and multi-pass rendering are presented, enabling the combination of shading and classification of volume data. Additionally, minor modifications to the data path are proposed such that multi-pass rendering can be avoided, thus increasing the overall achievable frame-rate. Furthermore, we demonstrate how to efficiently use general purpose hardware (a single-chip SIMD architecture) for volume rendering, providing much more flexibility than dedicated polygon graphics hardware. As a summary of the above described work, a novel low-cost special purpose hardware architecture that achieves superior image quality while providing an incomparable degree of flexibility is presented. en
dc.language.iso de de_DE
dc.publisher Universität Tübingen de_DE
dc.rights ubt-nopod de_DE
dc.rights.uri http://tobias-lib.uni-tuebingen.de/doku/lic_ubt-nopod.php?la=de de_DE
dc.rights.uri http://tobias-lib.uni-tuebingen.de/doku/lic_ubt-nopod.php?la=en en
dc.subject.classification Computergraphik , Elimination verdeckter Flächen ,Volumendaten / Visualisierung , Field programmable gate array de_DE
dc.subject.ddc 004 de_DE
dc.subject.other Occlusion Culling , 3D Texture Mapping , SIMD , Reconfigurable Hardeware de_DE
dc.subject.other Occlusion Culling , 3D Texture Mapping , SIMD , Reconfigurable Hardeware en
dc.title Occlusion Culling and Hardware Accelerated Volume Rendering en
dc.title Verdeckungsrechnung und hardwarebeschleunigte Volumenvisualisierung de_DE
dc.title Occlusion Culling and Hardware Accelerated Volume Rendering en
dc.type PhDThesis de_DE
dc.date.updated 2001-11-07 de_DE
dcterms.dateAccepted 2000-12-20 de_DE
utue.publikation.fachbereich Sonstige - Informations- und Kognitionswissenschaften de_DE
utue.publikation.fakultaet 7 Mathematisch-Naturwissenschaftliche Fakultät de_DE
dcterms.DCMIType Text de_DE
utue.publikation.typ doctoralThesis de_DE
utue.opus.id 292 de_DE
thesis.grantor 17 Fakultät für Informations- und Kognitionswissenschaften de_DE

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